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this is information on a product in full production. may 2014 docid18204 rev 7 1/36 m24m02-dr 2-mbit serial i2c bus eeprom datasheet - production data features ? compatible with all i 2 c bus modes: ?1 mhz ? 400 khz ? 100 khz ? memory array: ? 2 mbit (256 kbytes) of eeprom ? page size: 256 bytes ? additional write lockable page ? single supply voltage: ? 1.8 v to 5.5 v over ?40 c / +85 c ? write: ? byte write within 10 ms ? page write within 10 ms ? random and sequential read modes ? write protect of the whole memory array ? enhanced esd/latch-up protection ? more than 4 million write cycles ? more than 200-year data retention packages ? so8 ecopack2 ? ? wlcsp ecopack2 ? so8 (mn) 150 mil width wlcsp www.st.com
contents m24m02-dr 2/36 docid18204 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 lock identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 17 5.1.6 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 18 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid18204 rev 7 3/36 m24m02-dr contents 3 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.4 read identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.5 read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of tables m24m02-dr 4/36 docid18204 rev 7 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. so8n ? 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 31 table 15. m24m02-dr wlcsp package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
docid18204 rev 7 5/36 m24m02-dr list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so8 connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. wlcsp connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 10. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31 figure 16. m24m02-dr wlcsp package outline, bump side vi ew. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. m24m02-dr wlcsp recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
description m24m02-dr 6/36 docid18204 rev 7 1 description the m24m02-dr is a 2 mb i 2 c-compatible eeprom (electrically erasab le programmable memory) organized as 256 k 8 bits. the m24m02-dr can operate with a supply voltage from 1.8 v to 5.5 v, over an ambient temperature range of ?40 c / +85 c. the m24m02-dr offers an additional p age, named the identification page (256 bytes). the identification page can be used to store se nsitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram figure 2. so8 connections, top view 1. du: don't use (if connected, must be connected to v ss ) 2. see section 9: package mechanical data for package dimensions, and how to identify pin 1 table 1. signal names signal name function direction e2 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage - v ss ground - !) 3$! 6 ## -- $2 7# 3#, 6 33 % 3$! 6 33 3#, 7# $5 $5 6 ## % !)v
docid18204 rev 7 7/36 m24m02-dr description 35 figure 3. wlcsp connections 1. du: don't use (must be left floating) 2. see section 9: package mechanical data for package dimensions, and how to identify pin 1. -36 %xps vlgh ylhz ( 9vv 6&/ 6'$ :& 9ff '8 '8 7rsylhz expsv xqghuqhdwk ( 9vv 6&/ 6'$ 9ff '8 '8 :&
signal description m24m02-dr 8/36 docid18204 rev 7 2 signal description 2.1 serial clock (scl) the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be connected ( figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e2) this input signal is used to set the value that is to be looked for on the bit b3 of the 7-bit device select code. this input must be tied to v cc or v ss , to establish the device select code as shown in figure 4 . when not connected (left floating), this input is read as low (0). figure 4. chip enab le inputs connection 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disa bled to the entire memory array when write control ( wc ) is driven high. write operations are enabled when write control ( wc ) is either driven low or left floating. when write control ( wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
docid18204 rev 7 9/36 m24m02-dr signal description 35 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters ) . in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ) and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ). in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the power-on-reset threshold voltage, the device stops resp onding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
memory organization m24m02-dr 10/36 docid18204 rev 7 3 memory organization the memory is organized as shown below. figure 5. block diagram -36 7# #ontrollogic (ighvoltage generator )/shiftregister !ddressregister andcounter $ata register page 8decoder 9decoder )dentificationpage % 3#, 3$!
docid18204 rev 7 11/36 m24m02-dr device operation 35 4 device operation the device supports the i 2 c protocol. this is summarized in figure 6 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a dat a transfer can only be initia ted by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 6. i 2 c bus protocol 3#, 3$! 3#, 3$! 3$! 34!24 #ondition 3$! )nput 3$! #hange !)" 34/0 #ondition -3" !#+ 34!24 #ondition 3#, -3" !#+ 34/0 #ondition
device operation m24m02-dr 12/36 docid18204 rev 7 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is followed by noack can be fo llowed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
docid18204 rev 7 13/36 m24m02-dr device operation 35 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start conditio n. following this, the bus master s ends the device select code, shown in table 2 (on serial data (sda), most significant bit first). when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e2) input. the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the de vice does not match the device select code, it de selects itself from the bus, and goes into standby mode. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable msb address bits rw b7 b6 b5 b4 b3 b2 b1 b0 device select code when addressing the memory array 1010e2 (2) 2. e2 bit value is compared to the logic level applied on the input pin e2. a17 a16 rw device select code when addressing the identification page 1011e2 (2) xxrw
instructions m24m02-dr 14/36 docid18204 rev 7 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/ w bit (r w ) reset to 0. the device acknowledges this, as shown in figure 7 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. the 256 kbytes (2 mb) are addressed with 18 address bits, the 16 lower address bits being defined by the two address bytes and the most significant address bits (a17, a16) being included in the device select code (see table 4 ). when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any othe r time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 8 . table 3. most significant address byte a15 a14 a13 a12 a11 a10 a9 a8 table 4. least significant address byte a7 a6 a5 a4 a3 a2 a1 a0
docid18204 rev 7 15/36 m24m02-dr instructions 35 5.1.1 byte write after the device select code and the address by te, the bus master sends one data byte. if the addressed location is write-protected, by write control ( wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 7 . figure 7. write mode sequences with wc = 0 (data write enabled) 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 7# 3tart 0age7rite $evsel "yteaddr "yteaddr $atain 7# $atain !)d 0age7ritecontgd 7#contgd 3top $atain. !#+ 27 !#+ !#+ !#+ !#+ !#+ !#+ !#+ 27 !#+ !#+
instructions m24m02-dr 16/36 docid18204 rev 7 5.1.2 page write the page write mode allows up to 256 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a17/a8, are the same. if more bytes are se nt than will fit up to the end of the page, a ?roll-over? occurs, i.e. the by tes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the device if write control ( wc ) is low. if write control ( wc ) is high, the contents of the addressed memory location are not modified, an d each data byte is followed by a noack, as shown in figure 8 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bu s master generating a stop condition. figure 8. write mode sequences with wc = 1 (data write inhibited) 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 7# 3tart 0age7rite $evsel "yteaddr "yteaddr $atain 7# $atain !)d 0age7ritecontgd 7#contgd 3top $atain. !#+ !#+ !#+ ./!#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ ./!#+
docid18204 rev 7 17/36 m24m02-dr instructions 35 5.1.3 write identification page the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. it is writ ten by issuing the write identification page instruction. this instruction us es the same protocol and format as page write (into memory array), except for the following differences: ? device type identifier = 1011b ? msb address bits a17/a8 are don't care exce pt for address bit a10 which must be ?0?. lsb address bits a7/a0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 5.1.4 lock identification page the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is si milar to byte write (into memory array) with the following specific conditions: ? device type identifier = 1011b ? address bit a10 must be ?1?; all other address bits are don't care ? the data byte must be equal to the binary value xxxx xx1x, where x is don't care 5.1.5 ecc (error correction code) and write cycling the error correction code (ecc) is an internal logic function which is transparent for the i 2 c communication protocol. the ecc logic is implemented on each group of four eeprom bytes (1) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on group s of four bytes, a single byte can be written/cycled independently. in this case, th e ecc function also writes/cycles the three other bytes located in the same group (1) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be di stributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined table 9: cycling performance . 1. a group of four bytes is located at addresses [4 *n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
instructions m24m02-dr 18/36 docid18204 rev 7 5.1.6 minimizing write delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its intern al latches to the memory ce lls. the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to make use of this, a pollin g sequence can be used by the bus master. the sequence, as shown in figure 9 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 9. write cycle polling flowchart using ack 1. the seven most significant bits of the device se lect code of a random read (bottom right box in the figure) must be identical to the seven most significant bi ts of the device select code of the write (polling instruction in the figure). t?]??o ]v??}p??? $,h e?? k???]}v]? ???]vp?z uu}?? ^???}v]?]}v ]?o? ]?zzta < ???v z^ ek z^ ek z^??? ^?}? ?(}??z t?]????]}v 'hylfhvhohfw zlwk5: ^v??? vz]< z^ ek 6wduw&rqglwlrq }v?]v?z t?]?}???]}v }v?]v?z zv}uz}???]}v )luvwe\whrilqvwuxfwlrq zlwk5: douhdg\ ghfrghge\wkhghylfh
docid18204 rev 7 19/36 m24m02-dr instructions 35 5.2 read operations read operations are performed independently of the state of the write control ( wc ) signal. after the successful completion of a read oper ation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates t he data transfer and switches to its standby mode. figure 10. read mode sequences start dev sel * byte addr byte addr start dev sel data out 1 ai01105d data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequention random read start dev sel * data out1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
instructions m24m02-dr 20/36 docid18204 rev 7 5.2.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 10 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the r w bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/ w bit set to 1. the device acknowledges this, and outputs the byte addressed by the inter nal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition , as shown in figure 10 , without acknowledging the byte. note that the address counter value is defined by instructions accessing either the memory or the identification page. when accessing the identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value. when accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory, see section 5.2.1 ) instead of the current address read instruction. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 10 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.2.4 read identification page the identification page (256 bytes) is an addi tional page which can be written and (later) permanently locked in read-only mode. the identification page can be re ad by issuing an read identifica tion page instruction. this instruction uses the same protocol and form at as the random address read (from memory array) with device type identifier defined as 1011b. the msb address bits a17/a8 are don't care, the lsb address bits a7/a0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g.: when reading the identification page from location 100d, the number of bytes should be less than or equal to 156, as the id page boundary is 256 bytes).
docid18204 rev 7 21/36 m24m02-dr initial delivery state 35 5.2.5 read the lock status the locked/unlocked status of the identifica tion page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. the device returns an acknowledge bit if the identification page is unlocked, otherwise a noack bit if the identification page is locked. right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: ? start: the truncated command is not execut ed because the start condition resets the device internal logic, ? stop: the device is then set back into standby mode by the stop condition. 6 initial delivery state the device is delivered with all the memory array bits and identification page bits set to 1 (each byte contains ffh).
maximum rating m24m02-dr 22/36 docid18204 rev 7 7 maximum rating stressing the device outside the ratings listed in table 5 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small b ody, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the european directive on re strictions of hazardous substances (rohs directive 2011/65/eu of july 2011). c i ol dc output current (sda = 0) - 5 ma v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (2) 2. positive and negative pulses applied on different co mbinations of pin connections, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 ). - 3000 v
docid18204 rev 7 23/36 m24m02-dr dc and ac parameters 35 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. figure 11. ac measure ment i/o waveform table 6. operating conditions symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 7. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf scl input rise/fall time, sda input fall time - 50 ns input levels 0.2 v cc to 0.8 v cc v input and output timing reference levels 0.3 v cc to 0.7 v cc v table 8. input parameters symbol parameter (1) 1. characterized only, not tested in production. test condition min. max. unit c in input capacitance (sda) - - 8 pf c in input capacitance (other pins) - - 6 pf z l input impedance (e2wc ) (2) 2. e2 input impedance when the memory is selected (after a start condition). v in < 0.3 v cc 30 - k z h v in > 0.7 v cc 500 - k -36 6 ## 6 ## 6 ## 6 ## )nputandoutput 4imingreferencelevels )nputvoltagelevels
dc and ac parameters m24m02-dr 24/36 docid18204 rev 7 table 9. cycling performance symbol parameter test condition max. unit ncycle write cycle endurance (1) 1. the write cycle endurance is defined for group of four bytes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer. the write cycle enduranc e is defined by characte rization and qualification. t a 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle (2) 2. a write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. when usi ng the byte write, the page write or the write identification page, refer also to section 5.1.5: ecc (error corr ection code) and write cycling t a = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 10. memory ce ll data retention parameter test condition min. unit data retention (1) 1. for products identified by process letter k. the data retention behavior is checked in production, while the 200-year limit is defined from charac terization and qualification results. t a = 55 c 200 year
docid18204 rev 7 25/36 m24m02-dr dc and ac parameters 35 . table 11. dc characteristics symbol parameter test conditions (in addition to those in table 6 and table 7 ) min. max. unit i li input leakage current (e2, scl, sda) v in = v ss or v cc device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) v cc = 1.8 v, f c = 400 khz - 1 ma v cc = 2.5 v, f c =400 khz - 1 ma v cc = 5.5 v, f c =400 khz - 2 ma 1.8 v < v cc < 5.5 v, f c = 1 mhz - 2.5 ma i cc0 supply current (write) average value during t w , 1.8 v v cc 5.5 v -2 (1) 1. characterized only, not tested in production. ma i cc1 standby supply current device not selected (2) , v in = v ss or v cc , v cc = 1.8 v 2. the device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -3a device not selected (2) , v in = v ss or v cc , v cc = 2.5 v -5a device not selected (2) , v in = v ss or v cc , v cc = 5.5 v -5a v il input low voltage (scl, sda, wc ) 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc < 5.5 v ?0.45 0.30 v cc v v ih input high voltage (scl, sda, wc ) 1.8 v v cc < 2.5 v 0.75 v cc v cc +1 v 2.5 v v cc < 5.5 v 0.70 v cc v cc +1 v v ol output low voltage i ol = 1.0 ma, v cc = 1.8 v - 0.2 v i ol = 2.1 ma, v cc = 2.5 v - 0.4 v i ol = 3.0 ma, v cc = 5.5 v - 0.4 v
dc and ac parameters m24m02-dr 26/36 docid18204 rev 7 table 12. 400 khz ac characteristics symbol alt. parameter (1) 1. test conditions (in addition to t hose specified under o perating conditions and ac test measurement conditions in section 8: dc and ac parameters ). min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (2) 2. characterized only, not tested in production. t f sda (out) fall time 20 (3) 3. with c l = 10 pf. 120 ns t xh1xh2 t r input signal rise time (4) 4. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (4) ns t xl1xl2 t f input signal fall time (4) (4) ns t dxch t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (5) 5. the min value for t clqx (data out hold time) of the m24xxx devices offers a safe timing to bridge the undefined region of the falling edge scl. t dh data out hold time 100 - ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) requi red by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that r bus c bus time constant is within the values specified in figure 12. t aa clock low to next data valid (access time) 100- 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t wldl (7) 7. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (8) 8. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 10 ms t ns (2) pulse width ignored (input filter on scl and sda) - single glitch -80ns
docid18204 rev 7 27/36 m24m02-dr dc and ac parameters 35 table 13. 1 mhz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 400 - ns t xh1xh2 t r input signal rise time (1) 1. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fall times be less than 120 ns when f c < 1 mhz. (1) ns t xl1xl2 t f input signal fall time (1) (1) ns t ql1ql2 (2) 2. characterized only, not tested in production. t f sda (out) fall time 20 (3) 3. with c l = 10 pf. 120 ns t dxch t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 - ns t clqv (5) 5. t clqv is the time (from the falling edge of scl) requi red by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time cons tant is within the values specified in figure 13 . t aa clock low to next data valid (access time) - 450 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t wldl (6) 6. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (7)(2) 7. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 10 ms t ns (2) pulse width ignored (input filter on scl and sda) -80ns
dc and ac parameters m24m02-dr 28/36 docid18204 rev 7 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 13. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz aib "uslinecapacitorp& "uslinepull upresistor k )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! 2 bus # bus ns (ere2 bus # bus ns k ? p& 4he2x#timeconstant mustbebelowthens timeconstantlinerepresented ontheleft bus bus "uslinecapacitorp& "uslinepull upresistork -36 )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! (ere 2 bus # bus ns 2 bu s # bu s ns 4he2 bus # bus timeconstant mustbebelowthens timeconstantlinerepresented ontheleft
docid18204 rev 7 29/36 m24m02-dr dc and ac parameters 35 figure 14. ac waveforms ^> ^k? ^> ^/v ?o] ?>ys ?>yy ?,, ^?}? }v]?]}v ?,> ^??? }v]?]}v t?]??o ?t /??] ?o] ?y>y>? ^/v ?,> ^??? }v]?]}v ?y, ?>y ^ /v?? ^ zvp ?,, ?,> ^?}? }v]?]}v ^??? }v]?]}v ?y,y,? ^> ?,> ?>> ?>, ?y,y,? ?y>y>? ?y>y>? t ?t>> ?,t, ?,>
package mechanical data m24m02-dr 30/36 docid18204 rev 7 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
docid18204 rev 7 31/36 m24m02-dr package mechanical data 35 figure 15. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 14. so8n ? 8-lead pl astic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a ? ? 1.750 ? ? 0.0689 a1 ? 0.100 0.250 ? 0.0039 0.0098 a2 ? 1.250 ? ? 0.0492 ? b ? 0.280 0.480 ? 0.0110 0.0189 c ? 0.170 0.230 ? 0.0067 0.0091 ccc ? ? 0.100 ? ? 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 ? ? 0.0500 ? ? h ? 0.250 0.500 ? 0.0098 0.0197 k ? 0 8 ? 0 8 l ? 0.400 1.270 ? 0.0157 0.0500 l1 1.040 ? ? 0.0409 ? ? 62$ ( fff e h $ ' f ( k[? $ n pp / / $ *$8*(3/$1(
package mechanical data m24m02-dr 32/36 docid18204 rev 7 figure 16. m24m02-dr wlcsp package outline, bump side view 1. drawing is not to scale. table 15. m24m02-dr wlcsp package mechanical data (1) 1. preliminary data. symbol millimeters inches (2) 2. values in inches are converted fr om mm and rounded to four decimal digits. min typ max min typ max a 0.540 0.500 0.580 0.0213 0.0197 0.0228 a1 0.190 - - 0.0075 - - a2 0.350 - - 0.0138 - - b (ball diameter) 0.270 - - 0.0106 - - d 3.536 3.556 3.576 0.1392 0.1400 0.1408 e 1.991 2.011 2.031 0.0784 0.0792 0.0800 e - 0.500 - - 0.0197 - e1 - 2.100 - - 0.0827 - e2 - 1.000 - - 0.0394 - e3 - 1.400 - - 0.0551 - 3ideview "umpside ! ! $ e e e % e %?-%?6 !
docid18204 rev 7 33/36 m24m02-dr package mechanical data 35 figure 17. m24m02-dr wlcsp recommended footprint (b)3b9 pp pp pp pp pp ?pp
part numbering m24m02-dr 34/36 docid18204 rev 7 10 part numbering table 16. ordering information scheme example: m24m02-d r mn 6 t p /k device type m24 = i 2 c serial access eeprom device function m02-d = 2 mbit (256 kb 8 bits) eeprom with additional identification page operating voltage r = v cc = 1.8 v to 5.5 v package mn = so8 (150 mil width) (1) 1. rohs-compliant and halogen-free (ecopack2 ? ) cs = standard wlcsp (1) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option t = tape and reel packing blank = tube packing plating technology p = ecopack ? (rohs compliant) process (2) 2. the process letters apply to wlcsp devices only. the process letters appear on the device package (marking) and on the shipment box. please contact your nearest st sales office for further information. /k = manufacturing technology code
docid18204 rev 7 35/36 m24m02-dr revision history 35 11 revision history table 17. document revision history date revision changes 22-dec-2010 1 initial release. 09-feb-2011 2 updated: ? section 3.18: read identification page ? section 3.19: read the lock status ? figure 2: so8 connections ? table 6: absolute maximum ratings ? table 10: input parameters ? table 11: dc characteristics ? table 12: ac characteristics at 400 khz ? table 13: 1 mhz ac characteristics deleted: ? table 15 ?available m24m02-x products (package, voltage range, frequency, temperature grade)? . 09-aug-2011 3 updated figure 5: maximum r bus value versus bus parasitic capacitance (c bus ) for an i2c bus at maximum frequency f c = 1 mhz and table 11: dc characteristics . 07-feb-2012 4 updated: ? table 2: device select code ? table 3: most significant address byte ? table 4: least significant address byte . ? section 3.6: write operations ? section 3.8: page write 25-oct-2012 5 updated document template and text (minor changes). cycling updated to 4 million cycles and data retention updated to 200 years. added wlcsp packages. 04-jun-2013 6 document reformatted. removed information related to thin wlcsp package. updated: ? wlcsp package silhouette on cover page ? section 1: description ? figure 3: wlcsp connections ? note (1) under table 5: absolute maximum ratings . added figure 17: m24m02-dr wlcsp recommended footprint 23-may-2014 7 removed note on page 7, updated table 2: device select code , updated section numbering for section 5.2.4 and section 5.2.5 , updated note 1 on table 10: memory ce ll data retention , updated figure 17: m24m02-dr wlcsp recommended footprint .
m24m02-dr 36/36 docid18204 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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